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Integrated Circuit Systems, Inc.
ICS95V860
2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz)
Recommended Application: DDR Memory Modules / Zero Delay Fan Out Buffer Product Description/Features: * Low skew, low jitter PLL clock driver * 1 to 13 differential clock distribution (SSTL_2) * Feedback pins for input to output synchronization * PD# for power management * Spread Spectrum-tolerant inputs * Auto PD when input signal removed * 0C to 85C operation Switching Characteristics: * CYCLE - CYCLE jitter (>100MHz):<75ps * OUTPUT - OUTPUT skew: <70ps * DUTY CYCLE: 49% - 51%
Functionality
INPUTS AVDD PD# GND GND 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) H H L H H X CLK_INT L H X L H <20MHz) OUTPUTS PLL State CLK_INC CLKT CLKC FB_OUTT FB_OUTC H L X H L L H Z L H Z H L Z H L Z L H Z L H Z H L Z H L Z Bypassed/off Bypassed/off off on on off
Block Diagram
FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1
PD# I2C_SCL, I2C_SDA I2C_A0, I2CA1
Control Logic
CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4
FB_INT FB_INC CLK_INC CLK_INT
CLKT5 CLKC5
PLL
CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 CLKT10 CLKC10 CLKT11 CLKC11 CLKT12 CLKC12
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ICS95V860
Bottom View
1 2 A I2C_A0 CLKC0 B I2C_A1 VSS C FB_OUTT VSS D FB_OUTC VDD E FB_INT FB_INC F AVDD AGND G CLK_INT CLK_INC H CLKT12 VDD J CLKC12 VSS K I2C_SDA VSS L I2C_SCL CLKT11
3 CLKT0 VDD
4 CLKC1 VDD
5 CLKT1 VSS
6 CLKC2 VSS
7 CLKT2 VDD
8 CLKC3 VDD
9 CLKT3 VSS
Top View
VDD CLKC11
VDD CLKT10
VSS CLKC10
VSS CLKT9
VDD CLKC9
VDD CLKT8
VSS CLKC8
10 PD# VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD_I2C
11 VSS CLKC4 CLKT4 CLKC5 CLKT5 CLKC6 CLKT6 CLKC7 CLKT7 VSS VSS
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ICS95V860
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION B3, B4, B7, B8, C10, D2, D10, VDD G10, H2, H10, K3, K4, K7, K8 A11, B2, B5, B6, B9, B10, C2, E10, F10, J2, J10, K2, GND K5, K6, K9, K10, K11, L11 F1 F2 L10 A3, A5, A7, A9, C11, E11, G11, J11, L2, L4, L6, L8, H1 A2, A4, A6, A8, B11, D11, F11, H11, L3, L5, L7, L9, J1 G2 G1 D1 AVDD AGND VDD_I2C CLKT(12:0) PWR Power supply 2.5V
PWR
Ground
PWR PWR PWR OUT
Analog power supply, 2.5V A n a l o g gr o u n d . I2C VDD pin for I2C_SDA, SCL bias. "Tr ue" Clock of differential pair outputs.
CLKC(12:0)
OUT
"Complementar y" clocks of differential pair outputs.
CLK_INC CLK_INT FB_OUTC
IN IN OUT
"Complementar y" reference clock input "True" reference clock input "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC. "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error. Power Down. LVCMOS input I2C address bits. I2C bus data line. I2C bus clock line.
C1 E1 E2 A10 A1, B1 K1 L1
FB_OUTT FB_INT FB_INC PD# I2C_A0, I2C_A1 I2C_SDA I2C_SCL
OUT IN IN IN IN IN IN
General Description
ICS95V860 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to thirteen differential clock output pairs (CLKT[0:12], CLKC[0:12]) and one differential clock output feedback pair (FB_OUT, FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC) the input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When the input frequency is less than the operating frequency of the PLL (appproximately 20MHz), the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INC, CLK_INT).
(continued)
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ICS95V860
General Description (Continued)
The ICS95V860 is able to track Spread Spectrum Clock (SSC) for reduced EMI. The ICS95V860 is an I2C slave/receiver that supports standard and "fast" mode. The ICS95V860 I2C interface is compliant to "The I2C-Bus Specification", version 2.1 January 2000 Philips Semiconductors, except that I2C_SDA and I2C_SCL are not 5.0V tolerant, but have a maximum input voltage of 4.2V or VDDI2C + 0.6V, whichever is lower. Register bits control the enable for each output pair and a global enable bit (GLOBALEN#) disables all outputs except the feeback output pair. A low places the disabled output pair in a high impedance state. Outputs are active during power up and are guaranteed to be at the correct duty cycle and period after the clock stabilization time.
Device I2C address = 11001, A1, A0, R/W I C Table: Output Control Register
Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2 2
Pin # A2,A3 A4,A5 A6,A7 A8,A9 B11,C11 D11,E11 F11,G11 H11,J11
Name CLK0EN CLK1EN CLK2EN CLK3EN CLK4EN CLK5EN CLK6EN CLK7EN
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
I C Table: Output Control Register
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L8,L9 L6,L7 L4,L5 L2,L3 H1,J1 Pin # Name CLK8EN CLK9EN CLK10EN CLK11EN CLK12EN Reserved Reserved GLOBALEN# Control Function Output Control Output Control Output Control Output Control Output Control Reserved Reserved Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Enable 1 Enable Enable Enable Enable Enable Disable PWD 1 1 1 1 1 0 0 0
NOTE: GLOBALEN# does not tristate the feedback output pair. The PLL continues to run and maintains lock even though all other outputs are tri-stated Disable = Output in high-impedance state
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . -0.5V to 3.6V Logic Inputs (except SDA, SCL) . . . . . . . . . GND -0.5 V to V DD + 0.5 V Logic Inputs (SDA, SCL) . . . . . . . . . . . . . . . GND -0.5 V to VDDI2C + 0.6 V Ambient Operating Temperature . . . . . . . . . . 0C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
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ICS95V860
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current High Impedance Output Current Input Clamp Voltage High-level output voltage Low-level output voltage Input Capacitance4 Supply Voltage I2C Supply Voltage SYMBOL I IH I IL I DD2.5 I DDPD I OZ VIK VOH VOL CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0pf @ 200MHz Enable = Low, FIN = 0 MHz VDD = 2.7V, Vout=VDD or GND VDDQ = 2.3V Iin = -18mA IOH = -1 mA IOH = -12 mA IOL=1 mA IOL=12 mA VI = GND or VDD VDD - 0.1 1.7V 0.1 0.6 3.5 2.7 3.6 VDDQ/2 - 0.18 0.7 0.3 x VDD_I2C VDDQ + 0.6 VDD_I2C + 0.6 VDDQ VDDQ + 0.6 VDDQ + 0.6 VDDQ/2 + 0.15 VDDQ/2 + 0.2 -12 12 1 0 4 85 MIN 5 TYP MAX 5 290 200 10 -1.2 UNITS A A mA A A V V V V V pF V V V V V V V V V V V V V mA mA V/ns C
250
CIN VDDQ, AVDD VDD_I2C I2C VDD supply pin CLKT, CLKC, FB_INC VIL Low level input voltage PD#, I2C_A0, I2C_A1 VIL_I2C I2C_SDA, I2C_SCL CLKT, CLKC, FB_INC VIH High level input voltage PD# VIH_I2C I2C_SDA, I2C_SCL DC input signal voltage2 Differential input signal voltage3 Output differential crossvoltage Input differential crossvoltage High level output current Low level output current Input slew rate Operating free-air temperature VID VOX VIX I OH I OL SR TA VOH = 1.7V VOL = 0.6V DC - CLKT, FB_INT AC - CLKT, FB_INT
2.5 2.3 2.3 -0.3 -0.3 VDDQ/2 + 0.18 1.7 0.7 x VDD_I2C -0.3 0.36 0.7 VDDQ/2 - 0.15 VDDQ/2 - 0.2
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VT-VC] required for switching, where VT is the true input level and VC is the complementary input level. 4. Guaranteed by design, not 100% tested in production.
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ICS95V860
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Input clock frequency Input clock duty cycle CLK stabilization freqop dtin TSTAB 100 40 225 60 10 UNITS MHz % s
Switching Characteristics
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle to Cycle Jitter1 Static phase offset Output to Output Skew Duty cycle SYMBOL t PLH1 t PLL1 t EN t dis Tjit (per) t (jit_hper) t sl(i) t sl(o) Tcyc -Tcyc t spo Tskew DC2 CONDITION CLK_IN to any output CLK_IN to any output PD# to any output PD# to any output -75 -70 1 1 -75 -75 49 MIN TYP 5.5 5.5 5 5 75 70 4 2.5 75 75 70 51 MAX UNITS ns ns ns ns ps ps V/ns V/ns ps ps ps %
0
Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, where the cycle (tc) decreases as the frequency goes up.
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ICS95V860
Parameter Measurement Information VDD V(CLKC)
R = 60
R = 60 VDD/2 V(CLKC) ICS95V860 GND Figure 1. IBIS Model Output Load VDD/2 ICS95V860 Z = 60 C = 12 pF -V DD/2 R = 10 Z = 50 SCOPE
R = 50 V(TT) Z = 60 R = 10 Z = 50
C = 12 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit
R = 50 V(TT)
YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
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ICS95V860
Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( ) = N (N is a large number of samples) Figure 4. St atic Phase Offset
t ( ) n+1
Y X# YX Y X, FB_OUTC Y X, FB_OUTT t(SK_O) Figure 5. Output Skew
Y X, FB_OUTC Y X, FB_OUTT Y X, FB_OUTC Y X, FB_OUTT
t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter
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1 fO
8
ICS95V860
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t (hper_n) 1 fo t (hper_n+1)
t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter
80%
80% VID , VOD
Clock Inputs and Outputs
20% Rise tsl Fall tsl
20%
Figure 8. Input and Output Slew Rates
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ICS95V860
0.12 C C ROW A, COLUMN 1
A3 A2 b
11 10 9 8 7 6 5 4 3 2 1 A B C D
B
E
TOP VIEW
E F G H J K L
E1
A1 A D A D1
e
TYP.
SYMBOL A A1 A2 A3 b D D1 E E1 e
MIN. 1.00 0.165 0.16 0.675 0.25
MILLIMETER NOM. 1.10 0.20 0.20 0.70 0.30 7.00 BSC 5.00 BSC 7.00 BSC 5.00 BSC 0.50 BSC
MAX. 1.20 0.235 0.24 0.725 0.35
MIN. 0.039 0.006 0.006 0.027 0.010
INCH* NOM. 0.043 0.008 0.008 0.028 0.012 .276 BSC .197 BSC .276 BSC .197 BSC .0197 BSC
MAX. 0.047 0.009 0.009 0.029 0.014
* For Reference Only. Controlling dimensions in mm. ref.: AIT-R0072MK-01
Ordering Information
ICS95V860yHLF-T
Example:
ICS XXXX y H LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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